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quad, 12 - bit dac voltage output with readback data sheet dac8412 / dac8413 features +5 v to 15 v o peration unipolar or b ipolar o peration true v oltage o utput double - b uffered i nputs reset to minimum (dac8413) or c enter s cale (dac8412) fast b us a ccess t ime readback applications automatic t est e quipment digitally c ontrolled c alibration servo c ontrols process c ontrol e quipment functional block dia gram dgnd a0 a1 cs reset ldac 12 i/o port control logic data i/o r/w input reg a input reg b input reg c input reg d output reg a output reg b output reg c output reg d dac a dac b dac c dac d v logic v dd v refh v refl v ss v outa v outb v outc v outd 00274-001 figure 1. general description the dac8412 / dac8413 are quad, 12 - bit voltage output dacs with readback capability. built using a complementary bi cmos process, these monolithic dacs offer the user very high package density. output voltage swing is set by the two reference inputs v refh and v refl . by setting the v refl input to 0 v and v refh to a positive voltage, the dac provide s a unipolar positive output range. a similar configuration with v refh at 0 v and v refl at a negative voltage provide s a unipolar negative output range. bipolar outputs are configured by connecting both v refh and v refl to nonzero voltages. this method of setting output voltage range has advantages over other bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. digital controls allow the user to load or read back data from any dac, load any dac , and t r ansfer data to all dacs at one time. an active low reset loads all dac output registers to midscale for the dac8412 and zero scale for the dac8413. the dac8412/dac8413 are available in 28 - lead plastic dip, 28- lead c eram i c d i p, 28- lead p lcc , and 28- lead lcc packages. they can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 v to 15 v, and references from +2.5 v to 10 v. power dissi pation is less than 330 mw with 15 v supplies and o nly 60 mw with a +5 v supply. for mil - std - 883 applications, contact your local a nalog devices , inc. sales office for the dac8412/dac8413/883 data sheet , which specifies operation over the ? 55c to +125c temperature range. all 883 parts are also available on standard military drawings 5962 - 91 76401mxa through 76404m3a. digital input code (decimal) 0.500 0.125 512 linearity error (lsb) 0.375 ?0.125 ?0.250 ?0.375 ?0.500 0.250 0 +125c +25c ?55c v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = ?55c, +25c, +125c 1024 1536 2046 2548 2560 3072 4096 0 00274-002 figure 2 . inl vs. code over temperature rev. g document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analo g devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2000 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com
dac8412/dac8413 data sheet rev. g | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? arevision hi story ............................................................................. 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ............................................. 9 ? theory of operation ...................................................................... 14 ? introduction ................................................................................ 14 ? dacs ............................................................................................ 14 ? glitch ............................................................................................ 14 ? reference inputs ......................................................................... 14 ? digital i/o ................................................................................... 14 ? coding ......................................................................................... 14 ? supplies ........................................................................................ 15 ? amplifiers .................................................................................... 15 ? reference configurations .......................................................... 16 ? single +5 v supply operation .................................................. 17 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 20 ? revision history 4/13rev. f to rev. g changed reference low input current from 0 ma (min), 2 ma (typ), 2.75 ma (max) to ?2 .75 ma (min), ?2 ma (typ), 0 ma (max); table 1 ......................................................................... 3 changes to reference configurations section ........................... 17 9/09rev. e to rev. f updated figure numbering .............................................. universal removed figure 7 ............................................................................. 6 changes to ordering guide .......................................................... 20 6/07rev. d to rev. e updated format .................................................................. universal added cerdip package .................................................... universal changes to specifications section .................................................. 3 changes to absolute maximum ratings section ......................... 7 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 20 3/00rev. c to rev. d
data sheet dac841 2/dac8413 rev. g | page 3 of 20 specifications electrical character istic s v dd = +15.0 v, v ss = ? 15.0 v, v logic = +5.0 v, v refh = +10.0 v, v refl = ? 10.0 v, ? 40 c t a +85 c , unless otherwise note d. 1 table 1 . parameter symbol conditions min typ max unit accuracy integral nonlinearity error inl e g rade 0.25 0.5 lsb f g rade 1 lsb differential nonlinearity error dnl monotonic o ver t emperature ? 1 lsb min - scale error v zse r l = 2 k 2 lsb full - scale error v fse r l = 2 k 2 lsb min - scale temp erature c o efficient tcv zse r l = 2 k 15 ppm/c full - scal e temperature coefficient tcv fse r l = 2 k 20 ppm/c linearity matching adjacent dac matching 1 lsb reference positive reference input voltage range 2 v refl + 2.5 v dd ? 2.5 v negative reference inp ut voltage range 2 ? 10 v refh ? 2.5 v reference high input current i refh ? 2.75 +1.5 +2.75 ma reference low input current i refl ?2.75 ? 2 0 ma large signal bandwidth bw ? 3 db, v refh = 0 v to 10 v p -p 160 khz amplifier characteristics output current i out r l = 2 k , c l = 100 pf C 5 +5 ma settling time t s t o 0.01%, 10 v s tep, r l = 1 k 10 s slew rate sr 10% to 90% 2.2 v/ s analog crosstalk 72 db logic characteristi cs logic input high voltage v inh t a = 25 c 2.4 v logic input low voltage v inl t a = 25 c 0.8 v logic output high voltage v oh i oh = 0.4 ma 2.4 v logic output low voltage v ol i ol = ? 1.6 ma 0.4 v logic input current i in 1 a input capacitance c in 8 pf digital feedthrough 3 v refh = 2.5 v, v refl = 0 v 5 nv -s ec logic timing characteristics 3 , 4 chip select write pulse width t wcs 80 ns write setup t ws t wcs = 80 ns 0 ns write hold t wh t wcs = 80 ns 0 ns address setup t as 0 ns address hold t ah 0 ns load setup t ls 70 ns load hold t lh 30 ns write data setup t wds t wcs = 80 ns 20 ns write data hold t wdh t wcs = 80 ns 0 ns load data pulse width t ldw 170 ns reset pulse width t reset 140 ns chip select read pulse width t rcs 130 ns read data hold t rdh t rcs = 130 ns 0 ns read data setup t rds t rcs = 130 ns 0 ns data to high -z t dz c l = 10 pf 200 ns chip select to data t csd c l = 100 pf 160 ns
dac8412/dac8413 data sheet rev. g | page 4 of 20 parameter symbol conditions min typ max unit supply characteristics power supply sensitivity pss 14.25 v v dd 15.75 v 150 ppm/v positive supply current i dd v refh = 2.5 v 8.5 12 ma negative supply current i ss ? 10 ? 6.5 ma power dissipation p diss 330 mw 1 all supplies can be varied 5%, and operation is guaranteed. device is tested with nominal supplies. 2 operation is guaranteed over this reference range, but lin earity is neither tested nor guaranteed. 3 all parameters are guaranteed by design. 4 all input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. v dd = v logic = +5.0 v 5%, v ss = 0.0 v, v refh = +2.5 v, v refl = 0.0 v, v ss = C 5.0 v 5%, v refl = ?2.5 v, ?40 c t a +85c , unless otherwise note d. 1 table 2 . parameter symbol conditions min typ max units accuracy integral nonlinearity error inl e g rade 0.5 1 lsb f g rade 2 lsb v ss = 0.0 v, e g rade 2 2 lsb v ss = 0.0 v, f g rade 2 4 lsb differential nonlinearity error dnl monotonic o ver t emperature C 1 lsb min - scale error v zse v ss = ? 5.0 v 4 lsb full - scale error v fse v ss = ? 5.0 v 4 lsb min - scale error v zse v ss = 0.0 v 8 lsb full - scale error v fse v ss = 0.0 v 8 lsb min - scale temperature coefficient tcv zse 100 ppm/ c full - scale temperature coeffic ient tcv fse 100 ppm/ c linearity matching adjacent dac m atching 1 lsb reference positive reference input voltage range 3 v refl + 2.5 v dd ? 2.5 v negative reference input voltage range v ss = 0.0 v 0 v refh ? 2.5 v v ss = ? 5.0 v C 2.5 v refh ? 2.5 v reference high input current i refh code 0x000 C 1.0 +1.0 ma large signal bandwidth bw ? 3 db, v refh = 0 v to 2.5 v p - p 450 khz amplifier characteristics output current i out r l = 2 k , c l = 100 pf C 1.25 +1.25 ma settling time t s t o 0.01%, 2.5 v s tep, r l = 1 k 7 s slew rate sr 10% to 90% 2.2 v/ s logic characteristics logic input high voltage v inh t a = 25 c 2.4 v logic input low voltage v inl t a = 25 c 0.8 v logic output high voltage v oh i oh = 0.4 ma 2.4 v logic output low voltage v ol i ol = ? 1.6 ma 0.45 v logic input current i in 1 a input capacitance c in 8 pf logic timing characteristics 4 , 5 chip select write pulse w idth t wcs 150 ns write setup t ws t wcs = 150 ns 0 ns write hold t wh t wcs = 150 ns 0 ns address setup t as 0 ns address hold t ah 0 ns load setup t ls 70 ns load hold t lh 50 ns
data sheet dac8412/dac8413 rev. g | page 5 of 20 parameter symbol conditions min typ max units write data setup t wds t wcs = 150 ns 20 ns write data hold t wdh t wcs = 150 ns 0 ns load data pulse width t ldw 180 ns reset pulse width t reset 150 ns chip select read pulse width t rcs 170 ns read data hold t rdh t rcs = 170 ns 20 ns read data setup t rds t rcs = 170 ns 0 ns data to high-z t dz c l = 10 pf 200 ns chip select to data t csd c l = 100 pf 320 ns supply characteristics power supply sensitivity pss 100 ppm/v positive supply current i dd 7 12 ma negative supply current i ss v ss = ?5.0 v ?10 ma power dissipation p diss v ss = 0 v 60 mw v ss = ?5.0 v 110 mw 1 all supplies can be varied 5%, and operation is guaranteed. device is tested with v dd = 4.75 v. 2 for single-supply operation only (v refl = 0.0 v, v ss = 0.0 v). due to internal offset errors, inl and dnl are measured beginning at 0x005. 3 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 all parameters are guaranteed by design. 5 all input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. cs a 0/a1 t rds t rcs t rdh t as t ah t dz t csd r/w data out data valid high-z high-z 00274-003 figure 3. data output (read timing) a0/a1 reset ldac t wcs r/w cs data in t ws t wh t as t ah t ls t lh t wdh t wds t ldw t reset 00274-004 figure 4. data write (input and output registers) timing
dac8412/dac8413 data sheet rev. g | page 6 of 20 address 80 n s data1 valid data2 valid data3 valid data4 valid r/w cs data in ldac address two address three address four t ws t as t ls t wds t wh t lh t wdh 00274-005 address one figure 5 . single- buffer mode c s r /w addres s lda c dat a i n 80 n s t ws t as t ls t lh t ldw t wdh t wh t wds data1 vali d data2 vali d data3 vali d data4 vali d 00274-006 address one address two address three address four figure 6 . double- buffer mode
data sheet dac841 2/dac8413 rev. g | page 7 of 20 absolute maximum rat ings t a = +25 c , unless otherwise noted . table 3 . parameter rating v ss to v dd ? 0.3 v, +33.0 v v ss to v lo gic ? 0.3 v, +33.0 v v logic to dgnd ? 0.3 v, +7.0 v v ss to v refl ? 0.3 v, +v ss ? 2.0 v v refh to v dd +2.0 v, +33.0 v v refh to v refl +2.0 v, v ss ? v dd current into any v ss pin 15 ma digital input voltage to dgnd ? 0.3 v, v logic + 0.3 v digital o utput voltage to dgnd ? 0.3 v, +7.0 v operating temperature range ep, fp, fpc ?40c to +85c at, bt, btc ? 55 c to +125 c junction temperature 150 c storage temperatur e range ? 65 c to +150 c power dissipation package 1000 mw lead temperature jedec in dustry standard soldering j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indica ted in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case mounting conditions, that is, a device in socket. table 4 . thermal resistance package type ja jc unit 28- lead plastic dip (pdip) 48 22 c/w 28 - terminal ceramic leadless chip carrier (llc) 70 28 c/w 28 - lead plastic leaded chip carrier (pllc) 63 25 c/w 28 - lead ceramic dual in - line package (cerdip) 51 9 c/w esd caution
dac8412/dac8413 data sheet rev. g | page 8 of 20 pin configuration and fu nction descriptions v refh 1 v outb 2 v outa 3 v ss 4 v refl 28 v outc 27 v outd 26 v dd 25 dgnd 5 reset 6 ldac 7 v logic 24 cs 23 a0 22 db0 (lsb) 8 a1 21 db1 9 r/w 20 db2 10 db11 (msb) 19 db3 11 db10 18 db4 12 db9 17 db5 13 db8 16 db6 14 db7 15 00274-008 dac8412/ dac8413 top view (not to scale) 1282726 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 dgnd reset ldac db0 (lsb) db1 db2 db3 v dd v logic cs a0 a1 r/w db11 (msb) v ss v outa v outb v refh v refl v outc v outd db4 db5 db6 db7 db8 db9 db10 pin 1 indentfier 12 13 14 15 16 17 18 00274-009 dac8412/ dac8413 top view (not to scale) 00274-010 dac8412/ dac8413 top view (not to scale) 5 dgnd 6 reset 7 ldac 8 db0 (lsb) 9 db1 10 db2 11 db3 25 v dd 24 v logic 23 cs 22 a0 21 a1 20 r/w 19 db11 (msb) 26 v outd 27 v outc 28 v refl 1 v refh 2 v outb 3 v outa 4 v ss 18 db10 17 db9 16 db8 15 db7 14 db6 13 db5 12 db4 figure 7. pdip/cerdip figure 8. plcc figure 9. lcc table 5. pin function descriptions pin number mnemonic description 1 v refh high-side dac reference input. 2 v outb dac b output. 3 v outa dac a output. 4 v ss lower rail power supply. 5 dgnd digital ground. 6 reset reset input and output registers to all 0s, enabled at active low. 7 ldac load data to dac, enabled at active low. 8 db0 data bit 0, lsb. 9 db1 data bit 1. 10 db2 data bit 2. 11 db3 data bit 3. 12 db4 data bit 4. 13 db5 data bit 5. 14 db6 data bit 6. 15 db7 data bit 7. 16 db8 data bit 8. 17 db9 data bit 9. 18 db10 data bit 10. 19 db11 data bit 11, msb. 20 r/w active low to write data to dac. active high to readback previous data at data bit pins with v logic connected to 5 v. 21 a1 address bit 1. 22 a0 address bit 0. 23 cs chip select, enabled at active low. 24 v logic voltage supply for readback function. can be open circuit if not used. 25 v dd upper rail power supply. 26 v outd dac d output. 27 v outc dac c output. 28 v refl low-side dac reference input.
data sheet dac841 2/dac8413 rev. g | page 9 of 20 typical performance cha racteristics 1 ?1 6 0 11 10 9 8 7 12 maximum linearity error (lsb) v refh (v) v dd = +15v v ss = ?15v v refl = ?10v t a = 25c 00274-011 figure 10 . dnl vs. v refh 1 ?1 0 3 2 1 maximum linearity error (lsb) v refh (v) v dd = 5v v ss = 0v v refl = 0v t a = 25c 00274-014 figure 11 . inl vs. v refh 0.4 ?0.6 1000 ?0.4 0 0 ?0.2 0.2 200 t = hours of operation at 125c 400 600 800 full-scale error (lsb) x+3 x xC3 v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v 00274-015 figure 12 . full - scale error vs. time accelerated by burn - in 0 ?2 ?1 2 1 3 2 1 maximum linearity error (lsb) v refh (v) v dd = 5v v ss = 0v v refl = 0v t a = 25c 00274-012 figure 13 . dnl v s. v refh 0.3 0.1 0.2 10 8 6 12 maximum linearity error (lsb) v refh (v) v dd = +15v v ss = ?15v v refl = 0v t a = 25c 00274-013 figure 14 . inl vs.v refh x+3 x xC3 0.3 ?0.7 1000 ?0.5 0 ?0.1 ?0.3 0.1 200 t = hours of operation at 125c 400 600 800 zero-scale error (lsb) v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v 00274-016 figure 15 . zero - scale error vs. time accelerated by burn - in
dac8412/dac8413 data sheet rev. g | page 10 of 20 0.2 ?0.6 ?0.4 ?75 0 ?0.2 0 temperature (c) 75 150 full-scale error (lsb) v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v dac a dac d dac b dac c 00274-017 figure 16 . full - scale error vs. temperature 0.2 ?0.6 ?0.4 ?75 0 ?0.2 0 temperature (c) 75 150 zero-scale error (lsb) v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v dac a dac d dac c dac b 00274-018 figure 17 . zero - scale error vs. temperature digital input code (decimal) 0.37500 0.08375 0 512 linearity error (lsb) 0.26125 ?0.09375 ?0.18750 ?0.23125 ?0.37500 0.18750 0 1024 1536 2048 2560 3072 3584 4096 v refh = 10v v refl = 0v t a = 25c 00274-019 figure 18 . c hannel - to - channel matching (v supply = 15 v) 1.00 0.25 linearity error (lsb) 0.75 ?0.25 ?0.50 ?0.75 ?1.00 0.50 0 digital input code (decimal) 0 512 1024 1536 2048 2560 3072 3584 4096 v dd = 5v v ss = 0v v refh = 2.5v t a = 25c 00274-020 figure 19 . channel - to - channel matching (v supply = +5 v/gnd) 13 10 4 7 3 7 i dd (ma) v refh (v) 1 5 9 13 v dd = +15v v ss = ?15v v refl = ?10v 00274-021 figure 20 . i dd vs. v refh (a ll dacs high ) digital input code (decimal) 0.500 0.125 512 linearity error (lsb) 0.375 ?0.125 ?0.250 ?0.375 ?0.500 0.250 0 v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = ?55c, +25c, +125c 1024 1536 2048 2560 3072 3584 4096 0 00274-022 figure 21 . inl vs. code
data sheet dac8412/dac8413 rev. g | page 11 of 20 ?580ns 10 v trig'd 0v 1s/div 9.42s 1v/div ea v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-026 figure 22. positive slew rate ?1.96s 15.5m v 2mv/div trig'd ?4.5mv 2s/div 0 input ?5v 5v/div 18.04s v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-025 figure 23. settling time (negative) v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c ?1.96s 32.5m v 5mv/div trig'd ?17.5mv 2s/div 5v input 0 5v/div 18.04s 1 lsb error band 00274-024 figure 24. settling time (positive) ?580ns 10 v t rig'd 0v 1s/div 9.42s 1v/di v ea v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-027 figure 25. negative slew rate 2.0 0.5 1.5 ?0.5 1.0 0 i vrefh (ma) digital input code (decimal) 511 1023 1535 2047 2559 3071 3583 4095 0 v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-023 figure 26. i vrefh vs. code 0.6 1.0 inl (lsb) load resistance (k ? ) 0.8 0.4 0.2 0 ?0.2 0.01 0.1 1 10 100 v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-028 figure 27. inl vs. load resistance
dac8412/dac8413 data sheet rev. g | page 12 of 20 8 12 full-scale voltage (v) load resistance (k?) 10 6 4 2 0 0.01 0.1 1 10 100 v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-029 figure 28 . output swing vs. load resistance 10m 10 100k 10k 1k 100 ?10 0 ?30 ?50 ?70 gain (db) frequency (hz) 1m 0 v dd = +15v v ss = ?15v v refh = 0 100mv v refl = ?10v data bits = +5v 200mv p-p 00274-030 figure 29 . small signal response temperature (c) 10 ?10 150 ?6 2 ?2 6 75 0 power supply current (ma) v dd = +15v v ss = ?15v i dd i ss ?75 00274-031 figure 30 . power supply current vs. temperature 10 100k 10k 1k 100 60 80 40 20 power supply rejection ratio (db) frequency (hz) 1m 0 100 +psrr: v dd = +15v 1vp v ss = ?15v ?psrr: v dd = +15v v ss = ?15v 1v v refh = +10v all data 0 +psrr ?psrr 00274-032 figure 31 . psrr vs. frequency 0.10 10 noise density (v) noise frequency (hz) 1 0.01 0.001 1 10 100 1k 10k v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-033 figure 32 . noise density vs. noise frequency 40 ?40 25 ?20 ?30 ?25 ?20 0 ?10 10 20 30 20 15 10 5 0 ?5 ?10 ?15 v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c data = 0x000 v out (v) i out (ma) +i sc ?i sc 00274-034 figure 33 . i out v s. v out
data sheet dac841 2/dac8413 rev. g | page 13 of 20 20v/div m 200s a ch1 12.9mv 1 ch1 mean 66.19v v dd = +15v v ss = ?15v v refh = +10v v refl = ?10v t a = 25c 00274-035 figure 34 . broadband noise 6 ?6 5 25 15 ?5 ?15 ?25 20 10 0 ?10 ?20 ?4 ?2 0 2 4 v dd = +15v v ss = 0v v refh = +10v v refl = 0v t a = 25c data = 0x800 v out (v) i out (ma) +i sc ?i sc 00274-036 figure 35 . i out vs. v out ch2 1.86v 2 1 1v 4s 1v 10s glitch at dac output deglitcher output 00274-037 figure 36 . glitch and deglitched r esults
dac8412/dac8413 data sheet rev. g | page 14 of 20 theory of operation introduction the dac8412/dac8413 are quad, voltage output, 12-bit parallel input dacs featuring a 12-bit data bus with readback capability. the only differences between the dac8412/dac8413 are the reset functions. the dac8412 resets to midscale (code 0x800), and the dac8413 resets to minimum scale (code 0x000). the ability to operate from a single 5 v supply is a unique feature of these dacs. operation of the dac8412/dac8413 can be viewed by dividing the system into three separate functional groups: the digital i/o and logic, the digital-to-analog converters, and the output amplifiers. dacs each dac is a voltage switched, high impedance (r = 50 k), r-2r ladder configuration. each 2r resistor is driven by a pair of switches that connect the resistor to either v refh or v refl . glitch worst-case glitch occurs at the transition between half-scale digital code 1000 0000 0000 to half-scale minus 1 lsb, 0111 1111 1111. it can be measured at about 2 v s (see figure 36). for demanding applications such as waveform generation or precision instrumentation control, a deglitcher circuit can be implemented with a standard sample-and-hold circuit (see figure 37). when cs is enabled by synchronizing the hold period to be longer than the glitch tradition, the output voltage can be smoothed with minimum disturbance. a quad sample-and-hold amplifier, smp04, has been used to illustrate the deglitching result (see figure 36). s/h cs dacout 1 dacout dacout dacout 1 s/h hshs 00274-038 figure 37. data output (read timing) reference inputs all four dacs share common reference high (v refh ) and reference low (v refl ) inputs. the voltages applied to these reference inputs set the output high and low voltage limits of all four of the dacs. each reference input has voltage restrictions with respect to the other reference and to the power supplies. the v refl can be set at any voltage between v ss and v refh ? 2.5 v, and v refh can be set to any value between +v dd ? 2.5 v and v refl + 2.5 v. note that because of these restrictions, the dac8412 references cannot be inverted (that is, v refl cannot be greater than v refh ). it is important to note that the dac8412 v refh input both sinks and sources current. in addition, the input current of both v refh and v refl are code-dependent. many references have limited current-sinking capability and must be buffered with an amplifier to drive v refh . the v refl has no such special requirements. it is recommended that the reference inputs be bypassed with 0.2 f capacitors when operating with 10 v references. this limits the reference bandwidth. digital i/o see table 6 for the digital control logic truth table. digital i/o consists of a 12-bit bidirectional data bus, two registers select inputs, a0 and a1, a r/ w input, a reset input, a chip select ( cs ), and a load dac ( ldac ) input. control of the dacs and bus direction is determined by these inputs as shown in table 6. digital data bits are labeled with the msb defined as data bit 11 and the lsb as data bit 0. all digital pins are ttl/cmos compatible. see figure 38 for a simplified i/o logic diagram. the register select inputs a0 and a1 select individual dac registers a (binary code 00) through d (binary code 11). decoding of the registers is enabled by the cs input. when cs is high, no decoding takes place, and neither the writing nor the reading of the input registers is enabled. the loading of the second bank of registers is controlled by the asynchronous ldac input. by taking ldac low while cs is enabled, all output registers can be updated simultaneously. note that the t ldw required pulse width for updating all dacs is a minimum of 170 ns. the r/ w input, when enabled by cs , controls the writing to and reading from the input register. coding both dac8412/dac8413 use binary coding. the output voltage can be calculated by 4096 ) ( nvv vv refl refh refl out ? ? ?? where n is the digital code in decimal.
data sheet dac841 2/dac8413 rev. g | page 15 of 20 reset the reset function can be used either at power - up or at any t ime d uring dac operation. the reset function is independent of cs . this pin is active low and sets the dac output registers to either center code for the dac8412, or zero cod e for the dac8413. the reset - to - center code is most useful when the dac is configured for bipolar references and an output of 0 v after reset is desired. supplies supplies required are v ss , v dd , and v logic . the v ss supply can be set between ? 15 v and 0 v. v dd is the positive supply; its operating range is between 5 v and 15 v. v logic is the digital output supply voltage for the readback function. it is normally connected to +5 v. this pin is a logic reference input only. it does not supply cu rrent to the device. if the readback function is not being used , v logic can be left open - circuit. while v logic does not supply current to the dac8412, it does supply currents to the digital outputs when readback is used. amplifiers unlike many voltage outp ut dacs, the dac8412 features buffered voltage outputs. each output is capable of both sourcing and sinking 5 ma at 10 v , eliminating the need for external amplifiers when driving 500 pf or smaller capacitive load in most applications. these amplifiers ar e short - circuit protected. table 6 . dac8412/dac8413 logic table a1 a0 r/ w cs rs ldac input register output register m ode dac l l l l h l write w rite transparent a l h l l h l write write transparent b h l l l h l write write transparent c h h l l h l write write transparent d l l l l h h write hold write input a l h l l h h write hold write i nput b h l l l h h write hold write input c h h l l h h write hold write input d l l h l h h read hold read input a l h h l h h read hold read input b h l h l h h read hold read input c h h h l h h read hold read input d x x x h h l hold update all output registers all x x x h h h hold hold hold all x x x x l x all registers reset to mid scale /zero - scale 1 all x x x h x all registers latched to mid scale / zero - scale 1 all 1 dac8412 resets to midscale, and dac8413 resets to zero scale. l = l ogic l ow; h = l ogic h igh; x = d ont c are. input and o utput registers are transparent when asserted.
dac8412/dac8413 data sheet rev. g | page 16 of 20 wrdb0 wrdb1 wrdb2 wrdb3 wrdb4 wrdb5 wrdb6 wrdb7 wrdb8 wrdb9 wrdb10 rddacb rddaca wrdaca wrdacb rddacc wrdacc rddacd wrdacd readbackdatain_db10 readout readoutbar readbackdatain_db11 a1 a0 dgnd r/w db11..db0 v logic cs dac a dac b dac c dac d wrdb11 input register output register v refl v outd v outc v outa v outb rese t ldac v refh v dd v ss readback dataout_db11 00274-039 figure 38. simplified i/o logic diagram careful attention to grounding is important for accurate operation of the dac8412. this is not because the dac8412 is more sensitive than other 12-bit dacs, but because with four outputs and two references, there is greater potential for ground loops. because the dac8412 has no analog ground, the ground must be specified with respect to the reference. reference configurations output voltage ranges can be configured as either unipolar or bipolar, and within these choices, a wide variety of options exists. the unipolar configuration can be either positive or negative voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical. ref10 +15 v input output trim 10k ? 0.2f +10v operation + +15v op400 ?15v v refl v refh dac8412 or dac8413 0.1f //10f v dd v ss 00274-040 figure 39. unipolar +10 v operation +15v 1f 0.2f 39k? 6.2 ? 6.2 ? 0.2f +15v gain 100k ? balance 100k ? ad688 for 10v ad588 for 5v v dd v ss v refl v refh dac8412 or dac8413 0.1f //10f ?15v 5 or 10v operation 00274-041 figure 40. symmetrical bipolar operation figure 40 (symmetrical bipolar operation) shows the dac8412 configured for 10 v operation. see the ad688 data sheet for a full explanation of reference operation. adjustments may not be required for many applications since the ad688 is a very high accuracy reference. however, if additional adjustments are required, adjust the dac8412 full scale first. begin by loading the digital full-scale code (0xfff), and then adjust the gain adjust potentiometer to attain a dac output voltage of 9.9976 v. then, adjust the balance adjust to set the center-scale output voltage to 0.000 v.
data sheet dac8412/dac8413 rev. g | page 17 of 20 the 0.2 f bypass capacitors shown at the reference inputs in figure 40 should be used whenever 10 v references are used. applications with single references or references to 5 v may not require the 0.2 f bypassing. the 6.2 resistor in series with the output of the reference amplifier keeps the amplifier from oscillating with the capacitive load. this 6.2 resistor has been found to be large enough to stabilize this circuit. larger resistor values are acceptable, provided that the drop across the resistor does not exceed v be . assuming a minimum v be of 0.6 v and a maximum current of 2.75 ma, then the resistor should be under 200 for the loading of a single dac8412. using two separate references is not recommended. having two references can cause different drifts with time and temperature; whereas with a single reference, most drifts track. unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. this is preferable to using a reference and dividing down to the required value. for a 10 v full-scale output, the circuit can be configured as shown in figure 41. in this configuration, the full-scale value is set first by adjusting the 10 k resistor for a full-scale output of 9.9976 v. 10k ? 0.01f 10f ?15v g nd trim output voltage reference 0.2f v refl v refh dac8412 or dac8413 0.1f //10f zero to ?10v operation v dd v ss 00274-042 figure 41. unipolar C10 v operation figure 41 shows the dac8412 configured for C10 v to 0 v operation. a C10 v full-scale output voltage reference is connected directly to v refl for the reference voltage. single +5 v supply operation for operation with a 5 v supply, the reference voltage should be set between 1.0 v and 2.5 v for optimum linearity. figure 42 shows a ref43 used to supply a 2.5 v reference voltage. the headroom of the reference and dac are both sufficient to support a 5 v supply with 5% tolerance. v dd and v logic should be connected to the same supply. separate bypassing to each pin should also be used. 5 v input output gnd trim ref43 zero to 2.5v operation single 5v supply 10k? 0.2f v refl v refh dac8412 or dac8413 0.1f //10f 10f 0.01f v dd v ss 00274-043 figure 42. +5 v sing le-supply operation
dac8412/dac8413 data sheet rev. g | page 18 of 20 outline dimensions 1 28 5 11 18 botton view 19 25 26 4 12 0.15 (3.81) ref 0.075 (1.91) ref 0.028 (0.71) 0.022 (0.56) 0.300 (7.62) ref 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) ref 0.020 (0.51) min 0.05 (1.27) 0.095 (2.41) 0.075 (1.90) 0.458 (11.63) 0.442 (11.23) sq 0.458 (11.63) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 022106-a figure 43. 28-terminal cerami c leadless chip carrier [lcc] (e-28-1) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole leads. compliant to jedec standards ms-011 071006-a 0.100 (2.54) bsc 1.565 (39.75) 1.380 (35.05) 0.580 (14.73) 0.485 (12.31) 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.070 (1.78) 0.050 (1.27) 0.250 (6.35) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.700 (17.78) max 0.015 (0.38) 0.008 (0.20) 0.625 (15.88) 0.600 (15.24) 0.015 (0.38) gauge plane 0.195 (4.95) 0.125 (3.17) 28 114 15 figure 44. 28-lead plastic dual in-line package [pdip] wide body (n-28-2) dimensions shown in inches and (millimeters)
data sheet dac8412/dac8413 rev. g | page 19 of 20 compliant to jedec standards mo-047-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier 042508-a figure 45. 28-lead plastic leaded chip carrier [plcc] (p-28) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 28 114 15 0.610 (15.49) 0.500 (12.70) 0.005 (0.13) min 0.100 (2.54) max 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225(5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 15 0 pin 1 030106-a figure 46. 28-lead ceramic dual in-line package [cerdip] (q-28-2) dimensions shown in inches and (millimeters)
dac8412/dac8413 data sheet rev. g | page 20 of 20 ordering guide mode l 1 notes temperature range inl package descriptio n package option dac8412at/883c ?55c to +125c 0.75 28- lead ceramic dual in - line package [cerdip] q -28-2 dac8412bt/883c ?55c to +125c 1.5 28- lead ceramic dual in - line package [cerdip] q -28-2 dac8412btc/883c ?55c to +125c 1.5 28- terminal ceramic leadless chip carrier [lcc] e -2 8 -1 dac8412ep 2 ?40c to +85c 0.5 28- lead plastic dual in - line package [pdip] n -28- 2 dac8412epz 2 ?40c to +85c 0.5 28- lead plastic dual in - line package [pdip] n -28- 2 dac8412fp 2 ?40c to +85c 1 28- lead plastic dual in - line package [pdip] n -28- 2 dac8412fpc 2 ?40c to +85c 1 28- lead plastic leaded chip carrier [plcc] p -28 dac8412fpc - reel 2 ?40c to +85c 1 28- lead plastic leaded chip carrier [plcc] p -28 dac8412fpcz 2 ?40c to +85c 1 28- lead plastic leaded chip carrier [plcc] p -28 dac8412fpcz - reel 2 ?40c to +85c 1 28- lead plastic lea ded chip carrier [plcc] p -28 dac8412fpz 2 ?40c to +85c 1 28- lead plastic dual in - line package [pdip] n -28- 2 dac8413at/883c ?55c to +125c 0.75 28- lead ceramic dual in - line package [cerdip] q -28-2 dac8413bt/883c ?55c to +125c 1.5 28- lead ceramic dual in - line package [cerdip] q -28-2 dac8413btc/883c ?55c to +125c 1.5 28- terminal ceramic leadless chip carrier [lcc] e -28-1 dac8413ep 2 ?40c to +85c 0.5 28- lead plastic dual in - line package [pdip] n -28- 2 dac8413epz 2 ?40c to +85c 0.5 28- lead plastic dual in - line package [pdip] n -28- 2 dac8413fp 2 ?40c to +85c 1 28- lead plastic dual in - line package [p dip] n -28- 2 dac8413fpc 2 ?40c to +85c 1 28- lead plastic leaded chip carrier [plcc] p -28 dac8413fpc - reel 2 ?40c to +85c 1 28- lead plastic leaded chip carrier [plcc] p -28 dac8413f pcz 2 ?40c to +85c 1 28- lead plastic leaded chip carrier [plcc] p -28 dac8413fpc - reel 2 ?40c to +85c 1 28- lead plastic dual in - line package [pdip] n -28- 2 dac8413fpz 2 ?40c to +85c 1 28- lead plastic dual in - line package [pdip] n -28- 2 1 z = rohs compliant part. 2 if burn - in is required, these models are available in cerdip. contact sales. ? 2000 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00274 - 0 - 4/13(g)

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